Intel's Next-Gen Xeon Phi (Knights Landing) to Use Silicon Photonics

With new interconnect and high-bandwidth memory technology, Intel claims this will be the first serious step toward exascale

John Rath

June 24, 2014

3 Min Read
Intel's Next-Gen Xeon Phi (Knights Landing) to Use Silicon Photonics
Upcoming Knights Landing Xeon Phi (pictured) will be first to use silicon photonics, but the generation after that (Knights Hill) will use Omni-Path, which the company says is faster than InfiniBand (Photo: Intel)

Intel says it has re-architected a fundamental building block of high performance computing systems, announcing the next generation of its Xeon Phi processor (code named Knights Landing) with Micron's Gen2 Hybrid Memory Cube technology and a new interconnect technology called Omni Scale Fabric. This will be the first interconnect to take advantage of Intel's silicon photonics technology.

The company made the announcement at this week's International Supercomputing Conference in Leipzig, Germany, claiming that the upcoming chip will be the first serious step in the pursuit of exascale computing. While the current-generation Phi is a coprocessor, Knights Landing will be a stand-alone "bootable" chip.

Powered by more than 60 HPC-enhanced Silvermont cores, the next-gen Intel Phi is expected to deliver more than 3 TFLOPS of double-precision performance and three times the single-threaded performance compared with the current generation. Not due out for another year, it will be mounted either directly onto the motherboard or plugged in as a PCIe card.

Intel is a CPU leader in HPC, but tracks behind Nvidia in coprocessors for supercomputers. Although Intel-based systems account for 85 percent of the world's most powerful supercomputers on the June 2014 Top500 list, only 17 use Xeon Phi, versus 44 that use Nvidia coprocessors.

"Intel is re-architecting the fundamental building block of HPC systems by integrating the Intel Omni Scale Fabric into Knights Landing, marking a significant inflection and milestone for the HPC industry," said Charles Wuischpard, vice president and general manager of workstations and HPC at Intel. "Knights Landing will be the first true many-core processor to address today's memory and I/O performance challenges.

"It will allow programmers to leverage existing code and standard programming models to achieve significant performance gains on a wide set of applications. Its platform design, programming model and balanced performance makes it the first viable step towards exascale."

High-bandwidth memory

To help alleviate I/O bottlenecks, the upcoming Intel Phi processor will contain up to 16GB of high-bandwidth on-package memory, Intel developed jointly with Micron. It delivers five times the bandwidth of DDR4 memory, as well as better energy efficiency and density than current GDDR-based memory.

The on-package memory is based on Micron's Gen2 Hybrid Memory Cube Nand flash DRAM chip.

Supercharged by photonics

The introduction of Intel's silicon-photonics-based Omni Scale end-to-end interconnect will give a big boost to systems with Knights Landing processors when launched. It will be an inflection point in performance of HPC systems.

Developed using a combination of acquired intellectual property from Cray and QLogic, as well as Intel's own in-house innovation. Omni Scale will include a full product line offering consisting of adapters, edge switches, director switch systems and open-source fabric management and software tools.

The new interconnect is not Infiniband, although it is compatible with it. Through a TrueScale upgrade program the current Intel True Scale Fabric can be migrated to Intel Omni Scale Fabric, so customers can transition to new fabric technology without change to their applications.

Knights Landing coming to NERSC

In April the National Energy Research Scientific Computing Center (NERSC) announced an HPC installation, planned for 2016, that will serve more than 5,000 users and support more than 700 extreme-scale science projects. It will be take advantage of the next-gen Xeon Phi chips.

"We are excited about our partnership with Cray and Intel to develop NERSC's next supercomputer 'Cori,'" said Sudip Dosanjh, NERSC director. "Cori will consist of over 9,300 Intel Knights Landing processors and will serve as an on-ramp to exascale for our users through an accessible programming model.

"Our codes, which are often memory-bandwidth limited, will also greatly benefit from Knights Landing's high speed on-package memory. We look forward to enabling new science that cannot be done on today's supercomputers."

Corrected: The previous version of this article erroneously referred to the upcoming Knights Landing product as a coprocessor. Intel has notified us that it will be a standalone processor, and the article has been corrected accordingly. Data Center Knowledge regrets the error.

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