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RISC-V processor on HiFive Unleashed developer board. SiFive

RISC-V Summit Debuts to Showcase Open Source ISA

Vendors at the first annual RISC-V Summit announce new products built around the open source processor specification.

SANTA CLARA, Calif. -- A year or so ago you'd probably have trouble finding someone who knew anything about the open source silicon project RISC-V. Then SiFive, a startup built around the reduced instruction set architecture, raised over $143,000 in a crowdfunding campaign taking pre-orders for HiFive Unleashed, a $999 single-board computer (SBC) for developers featuring what was then the most powerful RISC-V system, the Freedom U540, a multi-core processor that clocks at 1.5 GHz.

That proved there was considerable developer interest in the project, and it served as notice that this open source processor architecture was ready to tackle a wide range of workloads. Within weeks after the SBCs were delivered, the Linux distributions Debian and Red Hat's Fedora announced they were working on ports to the architecture -- a feat that was accomplished by both distros in near record time.

By this time NVIDIA had already been on the RISC-V bandwagon for a couple of years, having announced in 2016 that it was using RISC-V for the next generation of the Falcon micro-controller for its GPUs. An ecosystem of companies had also been growing around the ISA, mostly centered around using the technology in embedded IoT devices, an area where the technology was already well-suited and poised to take on the likes of ARM.

This week there's further proof that RISC-V has arrived. Something over 1,000 professionals, mostly on the hardware side of tech, are attending the first ever RISC-V Summit at the Santa Clara Convention Center in Silicon Valley.

At a keynote on Tuesday, the conference's second day, Krste Asanovic, co-founder and chief architect at SiFive as well as board chair of the non-profit RISC-V Foundation which oversees the project's development, said that RISC-V interest and adoption is being motivated by the project's openness more than from its impressive specs in areas such as speed, scalability, and power use.

Not that openness and capability don't go hand-in-hand.

"Whatever's broken or missing in RISC-V is going to get fixed," he added. "Again, because of its open source nature."

That's a textbook example of the open source development model, because as user companies come on board and begin to develop products around the specification, they add features that are important to them, as well as fix issues that affect them.

In another keynote, Martin Fink, CTO at Western Digital which is in the process of shifting its entire line to RISC-V processors, announced the company has developed its first RISC-V core to be used in its products. In addition, it's working with SiFive and Barefoot Networks on OmniXtend, an open coherence standard for RISC-V, and has built an instruction set simulator (ISS) that will be released as open source.

Another announcement came from Patrick Johnson, a VP with chip maker Microchip Technology which acquired longtime RISC-V developer Microsemi earlier this year. During his keynote he revealed Microsemi's PolarFire SOC, which is being billed as the first system on a chip-based FPGA.

Although many expect RISC-V to eventually find a place in data center servers, some work remains to be done to make the technology ready for those workloads.


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