RISC-V Is On a Roll. Is It Ready to Take a Seat Alongside Intel, AMD, and Arm?

RISC-V International's CTO says the open source ISA is bound for the data center as CPU in everything from IoT to HPC.

Christine Hall

March 1, 2021

4 Min Read
BBC Doctor Who HiFive Inventor Kit
BBC Doctor Who HiFive Inventor KitRISC-V International

RISC-V, the emerging open source instruction set architecture for processors that have so far been used mostly as accelerators, is suddenly on a roll and appears about ready to become competitive in the CPU arena.

The most activity has been in the hacker space. A year ago about the only way to play around with a RISC-V processor was to spend $1,000 for a development board from the RISC-V-based startup SiFive. These days, SparkFun, BeagleBoard, Pine64, Rios, and others have either already released or are about to release single-board computers powered by RISC-V silicon, and at prices as low as $15. There's even a BBC Doctor Who-based RISC-V mini computer, meant for kids to learn coding and sold for under $100.

"That rollout is going to continue with lots of vendors," Mark Himelstein, CTO at RISV-V International, told DCK. "Some of them are small, like SparkFun, clearly an embedded kind of thing -- like the tiniest Raspberry Pi. Then the BeagleBoard stuff starts showing up as something you can run Linux on. You're gonna see people doing things through a whole range of deployments, first for development and then actually deploying these things."

Data Center Bound

RISC-V is already in the data center, and not only as accelerators, but pulling duty as CPUs. For example, some HPC networks use RISC-V to process data in transit. It also appears to be on the way to another role, powering servers, where its low power consumption could make it especially useful for edge deployments.

"There have been [RISC-V-based] cloud servers already," Himelstein said. "Alibaba does that already -- them and some other people."

Soon he expects to see the architecture powering everything from smartphones to HPC systems.

"I know people are working on that stuff, because they've talked at a bunch of our conferences," he said, "and they've come to our meetings asking about pieces that they care about that fit into those kinds of workloads."

According to Himelstein, the reason more RISC-V servers aren't already emerging has less to do with the architecture's readiness than with the time it takes hardware manufacturers to develop products and bring them to market. It can take a year or so to bring an embedded product to market, he said. It's more like five years for a server.

"It's the product runway that dictates that," he said. "People have been working on things for a while, so, as those time periods come to an end you're going to start seeing a lot of products out there with a lot of RISC-V in them.

"I think success begets success," he added. "When people see somebody else doing something, and doing something novel and unique, or something that advantages them, then they try to do it too."

Modular Design

Much of the work being done right now to help put RISC-V on equal footing with Intel, AMD, and Arm revolves around developing extensions, which are part of the chip's modular design. Extensions can be seen as plug-ins chip designers can use to add functions to a chip that can be called on by software when needed. While some extensions offer functions unique to RISC-V, others include functions found in other types of chips.

For RISC-V, this modular design is partly a way of escaping the technical debt that's baked into the design of other architectures. Since these functions can be pulled or redesigned as needed, they'll never be a burden that RISC-V chip makers will have to carry long term as part of their legacy.

Because some extensions are extremely complex and have the potential to negatively affect performance if not designed with care, they must go through a rigorous approval process. Until recently, this has included even simple and straightforward extensions that can easily be integrated into a chip's design without performance concerns.

For the latter, RISC-V International has developed a Fast Track program, unveiled last week, for streamlining approval of these small extensions. As the name suggests, Fast Track greatly reduces the time needed to have an extension approved.

"Fast Track maintains the necessary checks and balances to ensure extensions are properly designed and adhere to RISC-V’s architectural approach, while paving the way for RISC-V International to rapidly expand its set of standardized extensions," Greg Favor, co-founder and CTO of Ventana Micro Systems, explained in a statement.

Alongside Fast Track's announcement, the first extension to take advantage of the process, ZiHintPause, was introduced. It's an extension that software developers can activate to reduce a chip's power consumption under certain circumstances, an especially useful feature for IoT or edge devices where power concerns are an issue.

Hardware Freedom

Himelstein said that the same dynamics that drives developers to open source software is attracting hardware companies to adopt open source RISC-V.

"You're seeing more products being put out there and it's in everything from IoT to HPC," he said. "That's because RISC-V gives you freedom. It gives you freedom to choose the things you want; it gives you freedom from the constraints of some of the other architectures; it gives you freedom financially, at some level, on the stock to build the chip and do all those things.

"There's a lot of freedom it gives you, and people really like that. They learn to like that through Linux in the software world, and now they're going, 'Wow, I can do this in the hardware world. Oh my God, this is phenomenal.'"

About the Author(s)

Christine Hall

Freelance author

Christine Hall has been a journalist since 1971. In 2001 she began writing a weekly consumer computer column and began covering IT full time in 2002, focusing on Linux and open source software. Since 2010 she's published and edited the website FOSS Force. Follow her on Twitter: @BrideOfLinux.

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