AMD Ships First Server CPUs Built With 3D Die Stacking

The first application of new technology triples the size of Level 3 cache.

Max Smolaks, Senior Editor

March 21, 2022

2 Min Read
AMD EPYC Milan-X (half-delidded)

AMD has started shipping the first ever server CPUs built by overlaying individually manufactured chips on top of each other.

The new 7003 series processors – previously codenamed ‘Milan-X’ – are based on 3rd generation Zen architecture and are aimed at technical computing workloads like computational fluid dynamics, finite element analysis, electronic design automation, and structural analysis.

Thanks to die stacking, the new chips feature the industry’s largest Level 3 cache, totaling 768MB – three times more than what was previously available in high-end AMD CPUs.

Server CPUs embrace vertical growth

Die stacking is emerging as a way to continue delivering chip performance increases, as the industry faces the slowdown of Moore’s Law. Instead of making transistors smaller, and chip surfaces larger, die stacking breaks the CPU into elements called chiplets, places them on top of each other, and fuses them together.

AMD was one of the first companies to start using chiplets as an answer to CPU design limitations back in 2019.

With Milan-X, the company is demonstrating its vertical or ‘3D’ stacking capabilities – an approach that is also being embraced by Intel, which calls its die stacking tech ‘Foveros,’ and AI hardware startup Graphcore, among others.

Related:Tencent Cloud To Start Selling Its Own AMD-powered Servers

AMD’s latest CPUs are using the newly-acquired chip real estate to supersize Level 3 cache – a chunk of on-die memory that is faster than RAM, is shared by all cores, and is used by processors to improve performance by preventing bottlenecks caused by fetch and execute cycles.

In practice, this means faster performance in a variety of workloads, with HPC and simulation applications standing to gain the most; it is worth noting that according to AMD, 3D V-Cache can also benefit traditional desktop workloads, and even video games.

AMD EPYC Milan-X Delidded

AMD's Milan-X CPU die without the lid - note the additional layer of silicon elements appearing in pink/blue gradient.

Server CPUs equipped with 3D V-Cache feature between 16 and 64 cores, eight DDR channels, and deliver base frequencies of up to 3.05 GHz – while fitting in the familiar SP3 socket.

Servers sporting the new silicon will be available from manufacturing partners including Atos, Cisco, Dell, Gigabyte, HPE, Lenovo, QCT, and Supermicro.

The new CPUs are available immediately in the public cloud, as part of Microsoft Azure’s HBv3 instances that were officially launched earlier today.

“HBv3 VMs are the fastest adopted addition to the Azure HPC platform ever, and with performance gains of up to 80% on key HPC workloads from the addition of AMD 3D V-Cache, we are seeing a further increase in customer demand,” said Nidhi Chappell, general manager for HPC, AI, SAP, and Confidential Computing at Azure.

About the Author(s)

Max Smolaks

Senior Editor, Informa

Max Smolaks is senior editor at Data Center Knowledge, a leading online publication dedicated to the data center industry. A passionate technology journalist, Max has been writing about IT for a decade, covering startups, hardware, and regulation – across B2B titles including Silicon, DatacenterDynamics, The Register, and AI Business.

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