ARM (ARMH) announced the CoreLink CCN-504, an interconnection technology that will make it easier to harness large numbers of ARM cores to work together to solve computing problems. The new system can deliver up to one terabit of usable system bandwidth per second, accelerating communication between components – which could expand the types of applications that can take advantage of ARM’s low-power processors.
Lead licensees for the CoreLink CCN-504 launch include LSI and Calxeda, which recently announced a $55 million round of additional funding for advancing low-power computing in the web server market. CoreLink will support many-core enterprise solutions built using the ARM Cortex A15 MPCore processor and next generation 64-bit processors.
“Calxeda and ARM have been working closely to meet the demands of the data center since ARM’s initial investment in our company in 2008, and we are beginning to see the fruits that relationship,” said Barry Evans, co-founder and CEO, Calxeda. “We are already building our next generation data center-class solutions using this new ARM CoreLink technology, and think we will once again send shock waves across the industry when they are announced.”
ARM has also unveiled the new ARM CoreLink DMC-520 dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. It will provide a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. It is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan DDR4/3 PHY IP planned for introduction in 2013.
Supporting up to 16 cores on the same silicon die, the CCN-504 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems by enabling each processor in the system to access the other processor caches. This reduces the need to access off-chip memory, saving time and energy, which is a key enabler in systems based on ARM big.LITTLE processing, a new paradigm that can deliver both high-performance, required for content creation and consumption, and extreme power efficiency for extended battery life.
“As the amount of data used increases exponentially over the next 10-15 years, the CoreLink CCN-504 and DMC-520 will play an important role by providing high-performance system IP solutions for many-core applications,” said Tom Cronk, deputy general manager, processor division, ARM. “This ensures quality of service and coherent operation across the system, and enables SoC designers to efficiently prioritize and handle wide data flows with optimum latency.”
Mali-T600 GPU’s get optimized
ARM also introduced the first POP (Processor Optimization Pack) IP solution for ARM Mali-T600 series graphics processor units (GPUs). ARM’s POP IP is core-hardening acceleration technology that produces the best implementations of ARM processors in the fastest time-to-market. Mali GPUs go into a variety of end devices, including a wide range of smartphones, from high performance to mass market, as well as tablets and smart TVs. Implementing POP IP for these GPU’s results in superior performance density/watt, and significant silicon savings, with as much as 19 percent lower power than implementations that don’t use POP IP.
“As the industry moves toward 28nm, designers need options that can lower their risk and help them achieve the fastest time-to-market. ARM is pleased to bring the benefits that have been experienced with POP IP usage around Cortex process implementation to Mali GPUs,” said Pete Hutton, general manager, Media Processing Division at ARM. “POP IP for Mali GPUs is not about pre-determined benchmarks, it’s about giving our partners greater flexibility by leveraging ARM’s holistic approach to explore and find the right optimization customized to the specific end-application.”