On the one-year anniversary of the White House having launched its National Strategic Computing Initiative, the group’s Executive Council published a report detailing new and revised topics for collaboration between academic research, the private sector, and government agencies. In that report, NSCI presents its strategy for discovering a new way to resume the growth patterns for computing power first ascertained by Intel founder Gordon Moore in 1965.
Strategic Objective 3, as the NSCI report presents it, outlines a moon shot-like goal of “establishing, over the next 15 years, a viable path forward for future HPC (high-performance computing) systems even after the limits of current semiconductor technology are reached (the post-Moore’s Law era).”
Simply stating the objective this way represents a concession by the federally funded and managed agency that it is no longer possible, given the current constraints of physics, for transistors to be “crammed” (Moore’s word for it) onto semiconductor dies as small as they currently are. Intel, which currently produces Xeon processors using a 14 nm process, had a roadmap in place for 10 nm lithography, followed by 7 nm and 5 nm.
But last year, it had to begin delaying implementation of the 10 nm phase until 2017. And last March, the company was forced to retire its famous “tick-tock” production cadence, in favor of a strategy involving partnership with software and systems developers to find new ways to increase performance, at something approaching the levels that data centers have come to expect.
The NSCI is all in favor of partnership and collaboration. But with respect to finding a new track for sustained performance growth over the long haul, it’s looking to principles that, as of today, still sound like science fiction.
“The NSCI envisions a more heterogeneous future computing environment, where digital (von Neumann-based) computing is augmented by systems implementing alternative computing paradigms to efficiently solve specific classes of problems,” reads the group’s current report. “These alternative computational paradigms — whether quantum, neuromorphic or other alternatives — may solve some classes of problems that are intractable with digital computing, and provide more efficient solutions for some other classes of problems.”
Just four weeks ago, a consortium of the world’s semiconductor associations, including the U.S. Semiconductor Industry Association (SIA), issued its 2015 International Technology Roadmap for Semiconductors. (You might say they were a tad late.) In contrast to the NSCI, which has clearly assumed Moore’s Law has run its course, the ITRS consortium asserts that producers will be able to pick up the physics train from where it left off, by exploring the third dimension.
“Moore’s Law is now entering into a third phase,” the ITRS report reads, “characterized by vertical integration and performance specifications driven towards reduction of power in either the active or the stand-by nodes. . . In the next decade, ITRS 2.0 predicts that the advent of the third phase of scaling — ‘3D Power Scaling’ — will become the driver of the rejuvenated semiconductor industry.”
An example of this concept currently in production is Intel’s and Micron Technology’s Hybrid Memory Cube, currently co-branded as 3D XPoint. Micron is currently putting its 3D NAND technology to work in the production of NAND flash storage devices and solid-state drives. Here, layers of 2D memory are linked to one another by way of a type of via, or pathway through which electrons traverse the various layers [depicted at top]. It’s a surprisingly simple concept.
But the White House initiative is focused on the next step beyond, utilizing resources from the National Science Foundation, NASA, and other agencies to “invest in other, post-Moore’s Law technologies that have the potential to support the NSCI Strategic Objectives, as they are identified.”
