Intel has launched the Xeon E5-2600 v3 processor family, formerly code-named Grantley-EP, optimized and accelerated for the modern data center. In the "tick-tock" product cycle that Intel follows, the latest edition (tock) of the two-year-old E5-2600 portfolio brings the Haswell microarchitecture to the 22-nanometer Xeon. The E5-2600 v2 chips have accounted for more than 80 percent of Intel's server chip segments in recent quarters.
For the first time, Xeon chips for compute, storage and network workloads feature a single architecture. This creates efficiencies in hardware development and opens doors for simplified operating models.
The company made the announcement in conjunction with Intel Developer Forum in San Francisco which kicked off Monday.
Eighteen cores, DDR4 memory and PCI Express 3... but wait, there's more!
The EP in Grantley-EP stands for Efficient Performance, and Intel has packed a variety of enhancements into the chip, as well as extra ingredients to speed integrated components. Intel has increased the core count on the v3 line up to 18 cores and added support for PCI Express 3 and four fast lanes to Samsung's DDR4 memory. Balancing performance and efficiency Intel is offering 29 products across the E5-2600 v3 line, with six- or eight-core basic configurations, eight- or 12-core low-power options, 10- to 12-core advanced options and 10 SKUs in what it calls segment-optimized, ranging all the way up to 18 cores.
Making more custom SKUs than ever
Diane Bryant, senior vice president and general manager of Intel's Data Center Group, said the amount of custom SKUs the company has now either committed to developing or has been shipping to certain customers is 20. Each of these chips are "custom to a specific customer to meet their specific workload needs," she said at a press conference in San Francisco Monday.
One of these customers is Microsoft. Kushagra Vaid, general manager of server engineering at Microsoft, joined Bryant on stage Monday, to briefly talk about the CPU customization Intel has done for the customer.
For Microsoft, the chipmaker has designed accelerated encryption, faster compression and a larger number of cores than available in off-the-shelf Xeon SKUs.
With the Haswell microarchitecture Intel now also offers per core P-states (PCPS), which drives voltage up and down per core, delivering up to 36-percent reduction in CPU power, while allowing greater flexibility for workloads, according to the company. An integrated voltage regulator is now integrated into the die, which enables faster transitions between power states and works with operating systems, which will orchestrate core use management.
Intel's Cache Monitor is also a pretty big deal in the v3 line, allowing Cache QoS to provide information about individual VMs in cache and enabling IT automation to make better decisions about utilization. Intel notes that much of the performance improvements over the last generation, as much as 90 percent, are due to Advanced Vector Extensions 2.0 (AVX2). To help separate workloads and optimize processing for them independently, AVX2 and Intel Turbo Boost Technology 2.0 automatically allows processor cores to run faster than the rated AVX base frequencies if they are operating below power, current and temperature specification limits.
Also launching at the 2014 IDF is the server reference architecture for Intel's Open Network Platform, and the Intel Ethernet Controller XL710, code named Fortville. The XL710 is a part of the converged network adapter family, and delivers 40GbE in the form of quad 10GbE ports or up to two 40GbE ports. Network technologies is another key focus area in Intel's approach to driving performance and efficiency into all areas of the data center. Intel recently laid out $650 million for LSI's networking business.
Intel feels there are a number of new market opportunities for the v3 Xeon processor, beyond the targeted enterprise, cloud, storage, HPC and communications segments. One of the many optimization techniques for the v3 family is described by Intel as evolving the data center rack into a composable set of pooled and disaggregated resources. With infrastructure driven by application requirements, this rack scale architecture has hardware attributes exposed upward to the provisioning management layer - optimizing all aspects for the software-defined data center.
Next-generation Broadwell 14 nanometer chips are already ramping up and are quieter, cooler and have equal performance with less power required. This will help fuel Intel's huge efforts outside of the server - in mobile, wearable and other Internet of Things endeavors. Intel's willingness to customize architectures and processor solutions for high-volume, large cloud players will help keep demand high as well.
At a recent investor event by Intel CEO Brian Krzanich confirmed that the Cannonlake 10nm microarchitecture, due out in 2016, will not need to use extreme ultraviolet (EUV) lithography. Krzanich also mentioned the new E5-2600 v3 chips being compatible with DDR3, DDR4 and two 'other' memory technologies. There has been speculation that Intel may be getting into the memory business.