Fast Chips Accelerate The Data Center
June 6th, 2013 By: John Rath
Semiconductor news from ARM, Marvell and IBM as these innovators seek to advance communications and push data through the data center faster than ever before.
ARM announces AMBA 5 CHI SoC. ARM announced the AMBA 5 CHI (Coherent Hub Interface) specification, which will enable ARM Cortex-A50 series processors to work together in high-performance, coherent processing “hubs”, and to deliver the high data rates that are common in Enterprise markets, such as servers and networking. The new AMBA 5 CHI protocol is used by the ARMv8 architecture-based Cortex-A57 and Cortex-A53 processors and the CoreLink DMC-520 Dynamic Memory Controller. It is also used by the CoreLink CCN-504 Cache Coherent Network, which is capable of 1 Terabit/s data flows. The architecture introduces a layered model to allow implementations to separate communication and transport protocols, which enables the optimal trade-off between performance, power and area.
“To ensure that our silicon partners can rapidly deploy IP and SoCs implementing the AMBA 5 CHI protocol, ARM has worked closely with many partners across the SoC design ecosystem,” says Noel Hurley, vice president, Marketing and Strategy, Processor Division, ARM. “Through early engagement we have enabled our EDA partners to develop a wide range of verification IP, and debugging and performance analysis tools to accelerate the implementation of AMBA 5 CHI based SoCs.”
Marvell introduces AVANTA LP SoC. Marvell (MRVL) introduced the Marvell AVANTA LP System-on-Chip (SoC) family, based on ARM Cortex-A9 architecture, to meet the latest video/audio-centric interactive environment requirements in modern, high-speed internet networks. The new SoCs expand the Universal Passive Optical Networks (UPON) processor family and target the growing demand for optical network terminals (ONT) by presenting an elegant, power-efficient and highly integrated solution tailored to meet highly constrained, leading world telecoms system specifications.
Marvell also announced an additional member of the AVANTA LP family – 88F6650 UPON 800MHz Cortex-A9 SoC. The 88F6650 is a performance-optimized device, designed to reduce the ONT BOM cost structure by reaching the highest level of integration with an embedded packet processor, 6-Gigabit port switch, quad GE PHYs and fits two layer PCB designs. “Marvell proudly addresses both the PON and Smart Home markets with the new AVANTA LP series, enhancing the way consumers access their live immersive digital content anytime, anywhere,” said Winston Chen, vice president for the Smart Home Business Unit at Marvell.
“With Marvell’s advanced packet processor design and breakthrough data forwarding optimization, we provide global manufacturers, telecom operators and ISPs with unmatched data forwarding capabilities at unparalleled speed further driving the next era of the digital lifestyle for consumers around the world.”
IBM preps new wireless chip. IBM introduced the fifth generation of semiconductor technology specialized for high performance communications. Its latest silicon-germanium (SiGe) chip-making process is designed to enable ever-increasing amounts of data to flow through network backbones in applications such as Wi-Fi, LTE cellular, wireless backhaul and high speed optical communications. The new 9HP SiGe technology continues to put advanced capability in the hands of engineers who design chips for LTE cellular base stations, millimeter-wave wireless communication links, and next generation short and long-haul optical communications.
“As early adopters of IBM’s SiGe technology, Semtech has consistently pushed the envelope on what can be achieved in high-speed wired and wireless communications systems and in high performance analog devices,” said Charles Harper, Senior Vice President of Semtech’s Systems Innovation Group. “With today’s technology, Semtech is a leader in 40Gbps and 100Gbps Communications Systems and with IBM’s latest SiGe technology we believe we can emerge as a leader in several new analog segments where performance, integration and power are critical requirements.”