Tilera and Maipu Introduce 512-Core Router

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A wafer displaying Tilera chips. Tilera said this week that its technology was powering a new 512-core router from China' Maipu. (Image: Tilera)

Technology from next-generation chipmaker Tilera is powering a new 512-core router from Maipu, the largest enterprise router supplier in China, the companies said this week.

Maipu is introducing the MP8800, a high-end distributed router designed to scale gracefully from 64 cores to 512 cores, supporting a wide range of applications. Maipu is targeting the government, financial, banking, and utility industries with the 512-core MP8800 portfolio. The new router is now generally available and is shipping to customers.

“The rapid development and availability of the MP8800 once again proves the unique value of our many-core technology – high performance, low power and ease of programmability,” said Devesh Garg, founder, president and CEO, Tilera. “512 cores with this performance and in this form factor is a huge feat; we are thrilled that Maipu selected Tilera for its new product. We expect the new router family to expand the enterprise market with higher scalability many-core based solutions.”

Tilera uses a low-power, many-core approach. Tilera uses an architecture that eliminates the on-chip bus interconnect, a centralized intersection where information flows between processor cores or between cores and the memory and I/O. Instead, Tilera employs an on-chip mesh network to interconnect cores. Tilera says its architecture provides similar capabilties for its caching system, evenly distributing the cache system load for better scalability.

25Gbps throughput

Tilera also announced it has achieved unparalleled Suricata performance, surpassing 25Gbps throughput on the TILE-Gx processor.  Suricata is an open source Intrusion Detection and Prevention System (IDS/IPS) developed by the Open Information Security Foundation (OISF) to secure networks against next generation security threats. The performance was achieved on Tilera’s TILExtreme-Gx high density platform that packs 144 cores with 4 TILE-Gx36 processors in a compact 1Urack mountable device. The multi-threaded Suricata application was implemented using Tilera’s Multicore Development Environment (MDE) 4.0, a full-featured run time Linux environment for TILE-Gx processors.

“This is another example of the ground breaking capabilities TILE-Gx processors are delivering today,” said Garg. “We are the world’s first company to achieve 25 Gbps performance in a 1U form factor when implementing the standard Suricata Emerging Threats rule set.”

About the Author

John Rath is a veteran IT professional and regular contributor at Data Center Knowledge. He has served many roles in the data center, including support, system administration, web development and facility management.

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